Verigy 93k — Tester Manual !!link!!

This section explains how to map logical device pins to physical tester channels. It covers the setup of different pin types, such as High-Speed Digital, Analog, or Power Supply pins.

The manual typically divides the system into several key components: Running the SmarTest software environment.

If you want to dive deeper into a specific area of the 93k system, let me know: differences High-speed digital setup (multi-Gbps) Analog/Mixed-signal testing modules verigy 93k tester manual

Used for high-precision applications, this calibrates specific pins to the Device Under Test (DUT) interface board level, compensating for traces and socket parasitics.

Measuring setup/hold times and propagation delays. Advanced Troubleshooting Tips This section explains how to map logical device

The 93k platform is designed around a scalable architecture that allows for "per-pin" resources. Unlike traditional testers that share resources across multiple pins, the 93k provides dedicated timing, levels, and pattern memory for each channel. This ensures that complex System-on-Chip (SoC) devices can be tested with maximum precision.

Precise voltage levels are critical for CMOS logic. The manual details how to set VIHcap V sub cap I cap H end-sub VILcap V sub cap I cap L end-sub VOHcap V sub cap O cap H end-sub VOLcap V sub cap O cap L end-sub for various drive and receive modes. If you want to dive deeper into a

Executing patterns at speed to verify logic gates.

Providing the mechanical interface to probers or handlers. SmarTest Software Environment

The manual includes a comprehensive list of error codes. Running the "Check Health" diagnostic tool is the first step in troubleshooting any hardware failure, such as a blown fuse or a malfunctioning pin electronics (PE) card. Developing a Test Program